1. Technical Field
The present invention relates to phase locked loops and in particular to an ultra high frequency resolution fractional N synthesizer.
2. Related Art
Phase Locked Loops (PLLs) are control systems which are used to match the phase of an output signal to that of an input (reference) signal. FIG. 1 shows a block diagram of a prior art phase locked loop. Generally, phase locked loops include a phase detector 100, an oscillator 102, such as a voltage controlled oscillator (VCO), and a feedback network 104 connecting the programmable oscillator to the phase detector. The phase detector receives inputs of a reference signal 106 and the output of the feedback network. The phase detector outputs a signal based on the difference in phase between the two inputs, which is then sent to the oscillator. Based on the signal received from the phase detector, the oscillator outputs an output signal 108 which is also sent back to the phase detector through the feedback network. Using feedback, the phase locked loop automatically adjusts the oscillator to keep the output signal in phase with the reference signal.